Introducing to USART in AVR


The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device. The main features are:
• Full Duplex Operation (Independent Serial Receive and Transmit Registers)
• Asynchronous or Synchronous Operation
• Master or Slave Clocked Synchronous Operation
• High Resolution Baud Rate Generator
• Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits
• Odd or Even Parity Generation and Parity Check Supported by Hardware
• Data OverRun Detection
• Framing Error Detection
• Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter
• Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete
• Multi-processor Communication Mode
• Double Speed Asynchronous Communication Mode

AVR USART vs. AVR UART – Compatibility

The USART is fully compatible with the AVR UART regarding:
• Bit locations inside all USART Registers
• Baud Rate Generation
• Transmitter Operation
• Transmit Buffer Functionality
• Receiver Operation

However, the receive buffering has two improvements that will affect the compatibility in some special cases:
• A second buffer register has been added. The two buffer registers operate as a circular FIFO buffer. Therefore the UDR must only be read once for each incoming data! More important is the fact that the Error Flags (FE and DOR) and the ninth data bit (RXB8) are buffered with the data in the receive buffer. Therefore the status bits must always be read before the UDR Register is read. Otherwise the error status will be lost since the buffer state is lost.
• The Receiver Shift Register can now act as a third buffer level. This is done by allowing the received data to remain in the serial Shift Register (see Figure 69) if the buffer registers are full, until a new start bit is detected. The USART is therefore more resistant to Data OverRun (DOR) error conditions.

The following control bits have changed name, but have same functionality and register location:
• CHR9 is changed to UCSZ2
• OR is changed to DOR

Clock Generation

The clock generation logic generates the base clock for the Transmitter and Receiver. The USART supports four modes of clock operation: Normal asynchronous, Double Speed asynchronous, Master synchronous and Slave synchronous mode. The UMSEL bit in USART Control and Status Register C (UCSRC) selects between asynchronous and synchronous operation. Double Speed (asynchronous mode only) is controlled by the U2X found in the UCSRA Register. When using Synchronous mode (UMSEL = 1), the Data Direction Register for the XCK pin (DDR_XCK) controls whether the clock source is internal (Master mode) or external (Slave mode). The XCK pin is only active when using synchronous mode.

Internal Clock Generation – The Baud Rate Generator

Internal clock generation is used for the asynchronous and the synchronous master modes of operation. The USART Baud Rate Register (UBRR) and the down-counter connected to it function as a programmable prescaler or baud rate generator. The down-counter, running at system clock (fosc), is loaded with the UBRR value each time the counter has counted down to zero or when the UBRRL Register is written. A clock is generated each time the counter reaches zero. This clock is the baud rate generator clock output (= fosc/(UBRR+1)). The Transmitter divides the baud rate generator clock output by 2, 8, or 16 depending on mode. The baud rate generator output is used directly by the receiver’s clock and data recovery units. However, the recovery units use a state machine that uses 2, 8, or 16 states depending on mode set by the state of the UMSEL, U2X and DDR_XCK bits. Table below contains equations for calculating the baud rate (in bits per second) and for calculating the UBRR value for each mode of operation using an internally generated clock source.

Double Speed Operation (U2X)

The transfer rate can be doubled by setting the U2X bit in UCSRA. Setting this bit only has effect for the asynchronous operation. Set this bit to zero when using synchronous operation. Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively doubling the transfer rate for asynchronous communication. Note however that the Receiver will in this case only use half the number of samples (reduced from 16 to 8) for data sampling and clock recovery, and therefore a more accurate baud rate setting and system clock are required when this mode is used. For the Transmitter, there are no downsides.

External Clock

External clocking is used by the synchronous slave modes of operation. The description in this section refers to Figure 70 for details. External clock input from the XCK pin is sampled by a synchronization register to minimize the chance of meta-stability. The output from the synchronization register must then pass through an edge detector before it can be used by the Transmitter and Receiver. This process introduces a two CPU clock period delay and therefore the maximum external XCK clock frequency is limited by the following equation:
 Note that fosc depends on the stability of the system clock source. It is therefore recommended to add some margin to avoid possible loss of data due to frequency variations.

Synchronous Clock Operation

When Synchronous mode is used (UMSEL = 1), the XCK pin will be used as either clock input (Slave) or  clock output (Master). The dependency between the clock edges and data sampling or data change is the same. The basic principle is that data input (on RxD) is sampled at the opposite XCK clock edge of the edge the data output (TxD) is changed.

The UCPOL bit UCRSC selects which XCK clock edge is used for data sampling and which is used for data change. As Figure 71 shows, when UCPOL is zero the data will be changed at rising XCK edge and sampled at falling XCK edge. If UCPOL is set, the data will be changed at falling XCK edge and sampled at rising XCK edge.

source: datasheetatmega8535


Latch is a bacis component of memory element. Before you study more such as flip flop, register, counter, etc, you must know about latch.

1.       Basic Latch
We see that latch can be as memory element when its input S=’0’ and R=’0’.

2.       Gated SR Latch
Gated latch is latch which use control signal/clock. Because we use S and R input, we call this latch as Gater SR Latch.

3.       Gated D Latch
It has single data input, called D, and it stores its value on this input, under a control of the clock.

Fuse Setting for the Clock

Using External Clock or Internal Clock ?

If you use WinAVR to program the AVR microcontroller and you want to use internal clock or external clock, You should changes the fuse of microcontroller. Before learn about this, you should know about how to use WinAVR and Makefile. You can see my early article here.

When you has installed WinAVR, you had also installed avrdude in you computer. Avrdude is used to program the AVR.

Now, if you want to check fuse setting on your AVR:
-          you should connect your AVR to your computer using ponyser programmer (RS232 to AVR ISP), or stk500 (usb to AVR ISP), or other kinds of programmer.
-          run command prompt as administrator.
-          type: avrdude –c stk500 –p atmega16 –P com4 –v (in this sample, I use atmega16 and stk500 prgrammer, if you use ponyser, change stk500 to ponyser, the com port is found by trying the command. If com4 don’t work, change to com1, com2, or com3)
-          If it is right, you will see the picture below. 

-          The value of lfuse = 0xE1. By the fuse table from datasheet atmega below, we know that it’s the setting for using internal clock. 

-          If you want to use external clock, set the lfuse to 0xEF by type : avrdude –c stk500 –p atmega16 –P com4 –U hfuse:w:0xD9:m –U lfuse:w:0xEF:m
-          The result is on picture below. 

If you use high frequency, of course the program in your chip is running faster. So, the fuse setting is very important if you want to change the speed of program processing. Another thing, don’t forget to change F_CPU in your source code and Makefile file because the _delay_ms(long int x) function from WinAVR library, using F_CPU variable to calculate the duration of delay and has been adjusted to clock of the chip. F_CPU should be the same as clock of the chip.

For experiment, I make a program:
#include <avr/io.h>
#include <util/delay.h>
#define F_CPU 1000000UL
void main(void)
       DDRC=0xff; //PA and PC as output
       PORTC=0x00; //PC always low voltage
       while (1) //looping forever
              PORTA=0xf0; //PA7-4 high, PA3-0 low
              PORTA=0x0f; //PA7-4 low, PA3-0 high

I try it on my board for:
internalclock 1 Mhz and F_CPU 1 Mhz, internalclock 1 Mhz and F_CPU 16 Mhz, externalclock 16 Mhz and F_CPU 16 Mhz, and externalclock 16 Mhz and F_CPU 1 Mhz. The result is in video below.

 The normal delay is 500 ms, as that have been declared in program.

Basic of AVR Input Output


In this explanation and next others, I will use Atmega 8535/16/32. It is because this AVR series is commonly used by students and developer. But, sometime I will use Atmega 8 for some simpler case. Beside that, I also use C programming because it is easy to use and many people choose this programming language.
These are some superiority of Atmega 8535:
Advanced RISC Architecture
– 130 Powerful Instructions
– Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
– On-chip 2-cycle Multiplier
Nonvolatile Program and Data Memories
– 8K Bytes of In-System Self-Programmable Flash
Endurance: 10,000 Write/Erase Cycles
– Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
– 512 Bytes EEPROM
Endurance: 100,000 Write/Erase Cycles
– 512 Bytes Internal SRAM
– Programming Lock for Software Security
Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
– Real Time Counter with Separate Oscillator
– Four PWM Channels
– 8-channel, 10-bit ADC
8 Single-ended Channels
7 Differential Channels for TQFP Package Only
2 Differential Channels with Programmable Gain at 1x, 10x, or 200x for TQFP
Package Only
– Byte-oriented Two-wire Serial Interface
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparatoror
 And Many More
Let's Learn
Atmega 8535 has 32 I/O register. Port A, B, C, and D have 8 bit, so the total is 32 bit. If we want to make a pin working as an input pin, we set its DDR to ‘0’. But if we want to make a pin working as an output pin, we set its DDR to ‘1’.
When a port works as input, there are two options, making it as input with internal pull-up or making it as floating input. To activate the pull-up internal we set its PORT to ‘1’ but if we want make it as floating input we set its PORT to ‘0’.
When a port works as output, there are also two option, making it to have high voltage or to have low voltage. PORT is set to ‘1’ for high voltage and PORT is set to ‘0’ for low voltage.
Ok, let’s make a sample program for basic input output.
In programmer notepad or other source  editors and based on WinAVR. Please check this for explanation how to use WinAVR and AVR Studio.
Let’s make a C code:
#include <avr/io.h>
void main (void)
{ DDRA=0b00000000;
The explanation:

DDRA = 0b00000000, it makes 8 pin in PORTA to work as input.
PORTA=0b00001111, it makes PORTA.0 – PORTA.3 to use internal pull-up and PORTA.4 – PORTA.7 to be floating input.

DDRB= 0b00001111, it makes PORTB.0 – 3 to work as output and PORTA.4 –7 to work as input.
PORTB=0b00110011, it makes PORTA.0 –1 to have high voltage, PORTA.2 – 3 to have low voltage, PORTA.4 – 5 to use internal pull-up and PORTA.6 – 7 to be floating input.

DDRC=0b11111111, it makes 8 pin in PORTC to work as output.
PORTC=0b11110000, it makes PORTC0 –3 to have low voltage and PORTA4 –7 to have high voltage.

output of PORTD will be same as input to PORTA. To access the value of an input register we should use PIN not PORT. If PORTA0 – 3 are connected to Vcc and PORTA4 – 7 are connected to Ground, the output of PORTD0 – 3 are high and PORTD4 – 7 are low.

All bit in a I/O register can be access one by one for example: DDRA1, PORTC3, PIND5, etc. We can make PORTD3 = PINA5, DDRB1 = 0, etc.

Internal pull-up is usually activated when the input port is connected to switch. Floating input is usually used when the input port is connected with sensor.

In the program above, I use a macro, io.h. Why I use this macro? I use this because definition of PORT, PIN, and DDR are there. Beside that there are some function in this header file that will be usefull for our program in the next. Such as:

·         _BV(n); to set the n-th bit of a registert. e.g: DDRC = _BV(5) means DDRC5 = 1.
·         bit_is_clear(sfr, n); return value = 1, if the n-th bit of sfr (register) is clear. Clear means 0, Set means 1.
·         bit_is_set(sfr, n); return value = 0, if the n-th bit of sfr (register) is clear.
·         loop_until_bit_is_clear(sfr,n); do nothing until the n-th bit of register equal to ‘0’.
·         loop_until_bit_is_set(sfr,n); do nothing while the n-th bit of register equal to ‘0’.

Note: To be more expert, you can use AVR Studio to simulate a progarm. You can see characteristic and every changes in every register in AVR.